1. Field of the Invention
The present invention relates to a readout circuit, a solid state image pickup device using the same circuit, and a camera system using the same, and more particularly to a readout circuit for temporarily storing a plurality of output signals from a photoelectric conversion unit and reading out the plurality of output signals stored, and its driving method.
2. Related Background Art
With reference to FIG. 14, the description will be made of a conventional example and its problems.
FIG. 14 shows a view of an equivalent circuit for a solid state image pickup device to be used in a line sensor or an area sensor in a conventional example.
In the solid state image pickup device according to the conventional example shown in FIG. 14, each output from a plurality of pixels 101, (in the example shown in the Figure, pixels of 20 pieces px6 to px25 in total of 5 pieces (5 lines) in a vertical direction, and 4 pieces (4 columns) in a horizontal direction) arranged in a two-dimensional shape are held to a holding capacity 103 constituting a memory unit (holding unit) of a line memory once by the selection switch 102a via a vertical output line 102 provided in common with every line, thereafter signals held to the holding capacity 103 are read out in order via its line selection switch 104a to output to a horizontal common signal line 105, and output has been made by a read common amplifier 107 (105a in the Figure denotes a horizontal common signal line reset switch). Each switch 102a, 104a, 105a in the Figure is constituted by, for example, an nMOS transistor (G denotes a gate electrode; S, a source electrode; and d, a drain electrode).
In this case, output from the holding capacity 103 to the horizontal common signal line 105 is performed by capacity division of parasitic capacity CH (Ch) of a horizontal common signal line consisting of capacity CT (Ct) of the holding capacity 103 and parasitic capacity and the like of the horizontal common signal line 105. In other words, when reset voltage of the horizontal common signal line 105 is assumed to be Vchr and signal voltage of light signal to be outputted from the pixel 101 is assumed to be Vsig, voltage to be held at the holding capacity CT becomes Vsig+Vchr, and voltage V to be outputted to the horizontal common signal line 105 is represented by the following expression.
                    V        =                                                            Ct                ×                                  (                                      Vsig                    +                    Vchr                                    )                                            +                              Ch                ×                Vchr                                                    (                              Ct                +                Ch                            )                                =                                                    Ct                ×                Vsig                                            (                                  Ct                  +                  Ch                                )                                      +            Vchr                                              (        1        )            
As shown by the above-described expression (1), readout gain of the light signal is given by Ct/(Ct+Ch).
The capacity CH of the horizontal common signal line is constituted by wiring capacity of the wiring and source-drain capacity of a switch to be connected to the wiring.
Because of tendency toward multi-pixels and larger size of the solid state image pickup device in recent years, the source drain capacity is increased, the length of wiring becomes longer and the wiring capacity becomes larger, and the capacity CH of the horizontal common signal line tends to increase. As a result, there has been the problem that when the capacity CH of the horizontal common signal line is large, the readout gain lowers and the S/N ratio is deteriorated.
Also, when the holding capacity CT is made larger in order to secure the S/N ratio, there has been the problem that the area of the holding capacity 103 will become larger to make the chip size larger.
Also, in order to solve these problems, as disclosed in Japanese Patent Application Laid-Open No. 05-037715, which is Japanese Patent official gazette open to public inspection, it has been proposed to provide a plurality of horizontal common signal lines and common readout amplifiers for dividing into each horizontal common signal line for outputting. A number of transistors to be connected to the horizontal common signal lines is reduced, whereby the capacity Ch of the horizontal common signal line is made smaller.
However, there have been problems of an increase in a number of output pins, an increase in power consumption and the like due to the increase in the number of the readout amplifiers.
Also, in order to solve these problems, the present inventor, et al., have already proposed means in which as shown in FIG. 15, every two holding capacity 103 are made into a block and for every block (in the example shown in the Figure, first block B1, second block B2) there is provided a common switch called “second switch 109” via an intermediate node (common signal line) 112, whereby the capacity CH of the horizontal common signal line is made smaller. In order to control such a switch group, the horizontal scan circuit 104 in FIG. 15 is used, but the following problems have arisen on that occasion.
FIG. 16 shows driving timing of the circuit shown in FIG. 15, and its problems will be described.
In FIG. 16, upon reading out a signal held in the holding capacity CT1 (103) of the block B1, the first switch M11 (108) and the second switch M16 (109) are turned ON to read out the signal via the intermediate node 112, the horizontal common signal line 105 and a read common amplifier 106.
In other words, a horizontal common signal line reset switch 110 is turned ON at timing t1, the horizontal common signal line 105 is reset, the horizontal common signal line reset switch 110 is turned OFF at timing t2, and thereafter, the first switch M11 (108) and the second switch N16 (109) are turned ON at timing t3.
Similarly, on reading out a signal held by the holding capacity CT2 (103), the first switch M11 (108) is turned OFF at timing t4, the horizontal common signal line reset switch 110 is turned ON at timing t5 to reset the horizontal common signal line 105, the horizontal common signal line reset switch 110 is turned OFF at timing t6, and thereafter, in addition to the second switch M16 (109) which is ON at timing t7, the first switch M12 (108) is turned ON. Thereafter, the second switch M16 (109) is turned OFF at timing t8. Hereinafter, signals held by holding capacity CT3, CT4 of the next block for adjoining at similar driving timing will be read out.
At this time, deflection of control line of the first switch M11, M12 (108) and the second switch M16 (109) causes a problem that a difference in level occurs in the output. This cause is as follows.
A general layout for the above-described holding capacity, horizontal common signal line, and horizontal scanning circuit is that they are arranged such that the horizontal common signal line 105 is sandwiched between the holding capacity 103 and the horizontal scanning circuit 104. For this reason, a control line for controlling switches such as the first switch M11 (108) and the second switch M16 (109) is arranged so as to cross the horizontal common signal line 105. Specifically, it is as shown in FIGS. 15 and 16.
Hereinafter, the description will be made while bringing the layout schematic view shown in FIG. 17 into correspondence with the equivalent circuit view shown in FIG. 15. In FIGS. 17 and 18, the first line memory CT101 to CT116 (203) correspond to the holding capacity CT (103) in FIG. 15; the control unit CTL1, CTL2 (204), the horizontal scanning circuit 104 in FIG. 15; the second common signal line 205, the horizontal common signal line 105 in FIG. 15; the first common signal line 212, the intermediate node 112 in FIG. 15; the first switch M101 to M116 (208), the first switch M11 to M14 (108) in FIG. 15; and the second switch M201, M202 (209), the second switch M16, M15 (109) in FIG. 15 respectively. Reference numeral 220 denotes outgoing wiring for connecting between the control unit CTL1, CTL2 (204) and the second switch M201, M202 (209).
Pieces of the holding capacity CT (103) shown in FIG. 15 are converted into blocks every two pieces, whereas FIG. 17 shows an example in which the first line memories CT101 to CT116 (203) corresponding to the holding capacity CT (103) have been converted into blocks every eight pieces of capacity. In the example shown in FIG. 17, the first block B1 and the second block B2 are illustrated from the left side.
In FIG. 17, reference symbols a1 to a16 denote control lines for opening/closing the first switches M101 to M116 (208) connected to the first line memories 203 (holding capacity CT101 to CT116). In FIGS. 17 and 18, control lines for the second switches M201, M202 (209) are not shown. FIG. 18 shows a schematic view for a detailed layout including the first and second holding capacity CT101, CT102 of the first line memory 203 within the first block B1 shown in FIG. 17, and the second switch M201 (209) for selecting the first block B1.
With reference to the above-described FIG. 16, the description will be made of driving timing of circuits shown in FIGS. 17 and 18 and their problems.
In the conventional technique, in order to drive a control electrode of each switch, only positive signals have been supplied.
First, at the timing t1, in a state in which the second switch M201 (second switch M16) has been turned ON, the second common signal line 205 (horizontal common signal line) is reset. At timing t2, the first common signal line 212 (intermediate node) and the second common signal line 205 (horizontal common signal line) enters a floating state. At timing t3, the first switch M101 (first switch M11) is additionally turned ON. At this time, since the first and second common signal lines 212, 205 are floating, a control line a1 for reading out from the holding capacity CT101, the first one from the left of the first line memory 203 is turned ON, whereby the second common signal line 205 is deflected via parasitic capacity Ca1 between the outgoing wiring 220 and the control line a1. At timing t7, a control line a2 for reading out from the holding capacity CT102, the second one from the left of the first line memory 203 is turned ON, whereby the second common signal line 205 is deflected via parasitic capacity Ca2 between the outgoing wiring 220 and the control line a2.
At this time, since the parasitic capacity Ca1 between the outgoing wiring 220 and the control line a1 and the parasitic capacity Ca2 between the outgoing wiring 220 and the control line a2 result from their respective distances La1, La2, they satisfy a relation of Ca1>>Ca2, and also differ in an amount of deflection of output. In fact, since the deflection due to the parasitic capacity Ca2 can be substantially ignored, only the deflection due to the parasitic capacity Ca1 is observed.
As a result, when eight pieces of capacity have been converted into blocks as shown in FIGS. 17, 18, there occurs pattern noise every eight pieces of output=heterogeneity of output. In other words, on reading out signals from the holding capacity CT101, CT109 of the first and ninth ones (the extreme left line of the first block B1, the second block B2) from the left of the first line memory 203 in FIG. 17, there has been a problem that the voltage of the second common signal line 205 changes into high voltage.
Specifically, between the control line a2 and the second common signal line 205, there is overlapping capacity indicated by a portion o in FIG. 16 in addition to the parasitic capacity Ca2. If this capacity is assumed to be Cc, when a logical level of the control signal of the control line a2 changes from L level to H level, that is, when supply voltage=VDD changes in voltage, voltage change ΔVCH in the second common signal line 205 is represented as the following expression.ΔVCH≈VDD×(Ca2+Cc×2)/CH 
Accordingly, when the control voltage of the control line ai of i-th (for example, second to eighth from the left) other than the first and ninth ones from the left within the block in FIG. 17 has been caused to change, voltage change ΔVCHi in the second common signal line 205 is as follows.ΔVCHi≈VDD×(Cai+Cc×2)/CH 
However, Cai denotes parasitic capacity between the control line ai of i-th one from the left within the block, and the outgoing wiring 220 (CH denotes parasitic capacity of the second common signal line).
Also, as described above, Ca1>>Ca2 to Ca8.
Therefore, with respect to output of the holding capacity CT102 to CT108 of the second to the eighth ones from the left within the first block B1, a voltage difference ΔVCH of several mV develops on the second common signal line 205.ΔVCH≈VDD×Ca1/CH 
The above-described problem is a level at which a problem is conspicuously posed particularly in the solid state image pickup device. That is, the above-described voltage difference ΔVCH is at a level of several mV or less. In other words, it becomes a more serious problem in an analog circuit represented by the solid state image pickup device which handles several mV or 1 mV or less than a digital circuit having logical amplitude of several V.
In order to solve these problems, such a conventional technique is conceivable as control lines of switches and horizontal common signal lines are arranged on layers different from each other and between them, another wiring layer is inserted as a shielding layer, and since parasitic capacity of the horizontal common signal line is increased, there arise problems that the capacity division ratio becomes larger so that S/N characteristic is not improved among others.